Memory devices for non-volatile storage of information include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM. EEPROM devices have the advantage of electrical programming and erasing, achieved by charging and discharging actions controlled by the control gate. The actions also affect the conductivity of the channel between source and drain. One advantage of flash memory is its capacity for block-by-block memory erasure. The speed of memory erasure is fast, and normally takes just 1˜2 seconds for the complete removal of a whole block of memory. Another advantage of flash memory is low electric consumptions. The voltages of a control gate, a source, and a drain are adjusted to program or erase in a split-gate flash memory.
The performance of EEPROM devices is enhanced by providing a protrusion for the floating gate of the split-gate memory cell. Normally, the protrusion is formed by poly oxidation, that is, by thermally oxidizing the polysilicon layer of which the floating gate comprises. The polyoxide portion of the polysilicon floating gate is used as a hard mask to form a protrusion, so-called gate bird's beak, which in turn enhances Fowler-Nordheim (F—N) tunneling for the programming and erasing of an EEPROM cell. FIGS. 1A to 1C are cross-sectional diagrams illustrating a conventional split-gate flash memory process. In FIG. 1A, a gate oxide layer 12 is thermally grown over a silicon substrate 10, and a first polysilicon layer 14 is then formed thereon followed by the deposition of a silicon nitride layer 16. Next, a photoresist layer 18 is provided on the silicon nitride layer 16 and has a pattern corresponding to areas where a floating gate will be defined, and then the floating gate pattern is etched into the silicon nitride layer 16, thus forming an opening 19 where the underlying first polysilicon layer 14 is exposed. After removing the photoresist layer 18, as shown in FIG. 1B, the exposed portion of the first polysilicon layer 14 is oxidized to form a polyoxide layer 20. In FIG. 1C, the silicon nitride layer 16 is subsequently removed from the first polysilicon layer 14, and then the polyoxide layer 20 serves as a hard mask to remove the first polysilicon layer 14 except the portion 14a that is covered by the polyoxide layer 20.
As well known in the art, the step of patterning the floating ate 14a is usually accomplished by main etch followed by over-etch, and therefore the corner edge 15 is usually rounded off, which is not desirable for achieving fast program erase speed. For the traditional method employing a local oxidation of silicon (LOCOS) process to form a LOCOS polyoxide, the sharpness of the floating-gate tip is no longer satisfactory, and it becomes more difficult to control the “bird's beak” length which impacts the height and angle of the poly tip. The poor shape of the poly tip considerably reduces yield and reliability. Several methods of improving the corner edge of the floating gate are disclosed in the prior art. U.S. Pat. No. 6,242,308 to Hsieh et al incorporated herein by reference, describes a method of forming poly tip to improve erasing and programming speed split gate flash. U.S. Pat. No. 6,090,668 to Hsieh et al incorporated herein by reference, describes a method of using a top-oxide as a hard mask to form floating gate. U.S. Pat. No. 6,410,957 to Hsieh et al incorporated herein by reference, describes a method of forming poly tips by smiling effect mechanism. None of the cited prior art teaches a simple process approach to improve the sharpness and height of the floating-gate tip for enhanced Fowler-Nordheim (F—N) tunneling.